| No. |
Part Name |
Description |
Manufacturer |
| 1 |
DDU8C3 SERIES |
5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
Data Delay Devices Inc |
| 2 |
FAR FAMILY (C3 SERIES M/N TYPE) |
Piezoelectric Resonator (4 to 20 MHz) |
Fujitsu Microelectronics |
| 3 |
IDT82V3011 |
T1/E1/OC3 WAN PLL with Single Input Reference Clock |
IDT |
| 4 |
IDT82V3012 |
T1/E1/OC3 WAN PLL with Dual Input Reference Clock |
IDT |
| 5 |
IDT82V3155 |
T1/E1/OC3 WAN PLL with Dual Input Reference Clock and 155MHz Output |
IDT |
| 6 |
IDT82V3155PVG |
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS |
IDT |
| 7 |
M38C34ECAXXXFP |
38C3 Series Microcontrollers: On-ChipSegment LCD Drivers with A-D Converter |
Mitsubishi Electric Corporation |
| 8 |
MT9044 |
Dual reference frequency selectable Digital PLL with multiple clock outputs for T1/E1 (ITU-T G.812 type IV), Stratum(3, 4, 4E) and STS-3/OC3 systems |
Zarlink Semiconductor |
| 9 |
MT9044AL |
T1/E1/OC3 System Synchronizer |
Mitel Semiconductor |
| 10 |
MT9044AP |
0.3-7.0V; T1/E1/OC3 system synchronizer. For synchronization and timing control for multitrunk T1, E1 and STS-3/OC3 systems, ST-BUS clock and frame pulse sources |
Mitel Semiconductor |
| 11 |
MT9044AP |
0.3-7.0V; T1/E1/OC3 system synchronizer. For synchronization and timing control for multitrunk T1, E1 and STS-3/OC3 systems, ST-BUS clock and frame pulse sources |
Mitel Semiconductor |
| 12 |
MT9045 |
Dual reference frequency selectable 3.3V Digital PLL with multiple clock outputs for T1/E1 (ITU-T G.812 type IV), Stratum( 3, 4, 4E) and STS-3/OC3 systems |
Zarlink Semiconductor |
| 13 |
MT9045AN |
T1/E1/OC3 System Synchronizer |
Zarlink Semiconductor |
| 14 |
QL3012-0PL84M |
12,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 15 |
QL3012-1PL84M |
12,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 16 |
QL3012-2PL84M |
12,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 17 |
QL3025-0PQ208M |
25,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 18 |
QL3025-1PQ208M |
25,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 19 |
QL3025-2PQ208M |
25,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 20 |
QL3040-0PQ208M |
40,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 21 |
QL3040-1PQ208M |
40,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 22 |
QL3040-2PQ208M |
40,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 23 |
QL3060-0PQ208M |
60,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 24 |
QL3060-1PQ208M |
60,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 25 |
QL3060-2PQ208M |
60,000 usable PLD gate pASIC3 FPGA combining high performance and high density. |
QuickLogic |
| 26 |
TZA3001 |
SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
Philips |
| 27 |
TZA3004 |
SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
Philips |
| 28 |
TZA3005H |
SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
Philips |
| 29 |
TZA3030 |
SDH/SONET STM1/OC3 optical receiver |
Philips |
| 30 |
TZA3030HL |
SDH/SONET STM1/OC3 optical receiver |
Philips |
| | | |
