| No. |
Part Name |
Description |
Manufacturer |
| 1 |
74LS11 |
Triple 3-Input AND gate |
Fairchild Semiconductor |
| 2 |
74LS11 |
Triple 3-Input AND Gate |
Fairchild Semiconductor |
| 3 |
74LS11 |
Triple 3-Input AND gates |
IPRS Baneasa |
| 4 |
74LS11 |
Triple 3-Input AND Gates |
IPRS Baneasa |
| 5 |
74LS112 |
Dual JK Negative Edge-Triggered Flip-Flop |
Fairchild Semiconductor |
| 6 |
74LS112 |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset/ Clear/ and Complementary Outputs |
Fairchild Semiconductor |
| 7 |
74LS112 |
Dual J-K Negative-edge-triggered Flip-Flops(with Preset and Clear) |
Hitachi Semiconductor |
| 8 |
74LS112 |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
Motorola |
| 9 |
74LS112 |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR |
Texas Instruments |
| 10 |
74LS113 |
Dual JK Edge-Triggered Flip-Flop |
Fairchild Semiconductor |
| 11 |
74LS114 |
Dual JK Negative Edge-Triggered Flip-Flop (With Common Clocks and Clears) |
Fairchild Semiconductor |
| 12 |
DL011D |
3 NAND gates with 3 inputs each (TTL low-power Schottky series), possibly equivalent SN74LS11N |
RFT |
| 13 |
DL112D |
Dual JK negative triggered flip-flop (TTL low-power Schottky series), possibly equivalent SN74LS112N |
RFT |
| 14 |
DM74LS11 |
Triple 3-Input AND Gate |
Fairchild Semiconductor |
| 15 |
DM74LS11 |
Triple 3-Input AND Gate |
National Semiconductor |
| 16 |
DM74LS112A |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs |
Fairchild Semiconductor |
| 17 |
DM74LS112A |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear and Complementary OP |
National Semiconductor |
| 18 |
DM74LS112ACW |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
Fairchild Semiconductor |
| 19 |
DM74LS112AM |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
Fairchild Semiconductor |
| 20 |
DM74LS112AM |
7 V, dual negative-edge-triggered master-slave J-K flip-flop with preset, clear and complementary output |
National Semiconductor |
| 21 |
DM74LS112AMX |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
Fairchild Semiconductor |
| 22 |
DM74LS112AN |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset/ Clear/ and Complementary Outputs |
Fairchild Semiconductor |
| 23 |
DM74LS112AN |
7 V, dual negative-edge-triggered master-slave J-K flip-flop with preset, clear and complementary output |
National Semiconductor |
| 24 |
DM74LS113A |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Complementary Outputs |
National Semiconductor |
| 25 |
DM74LS114A |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset and Common Clear, Common Clock adn Complementary Outputs |
National Semiconductor |
| 26 |
DM74LS11E |
Triple 3-Input AND Gates |
National Semiconductor |
| 27 |
DM74LS11J |
Triple 3-Input AND Gates |
National Semiconductor |
| 28 |
DM74LS11M |
Triple 3-Input AND Gate |
Fairchild Semiconductor |
| 29 |
DM74LS11M |
Triple 3-Input AND Gates |
National Semiconductor |
| 30 |
DM74LS11N |
Triple 3-Input AND Gate |
Fairchild Semiconductor |
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