No. |
Part Name |
Description |
Manufacturer |
1 |
2SJ125 |
150mW SMD J-FET (Field-Effect Transistor), maximum rating: 50V Vgdo, -10mA Ig, -1 to -12 mA Idss. |
Isahaya Electronics Corporation |
2 |
2SK433 |
150mW SMD J-FET (Field-Effect Transistor), maximum rating: -50V Vgdo, 10mA Ig, 0.6to 12 mA Idss. |
Isahaya Electronics Corporation |
3 |
2SK492 |
150mW SMD J-FET (Field-Effect Transistor), maximum rating: -50V Vgdo, 10mA Ig, 1 to 12 mA Idss. |
Isahaya Electronics Corporation |
4 |
54LS109 |
Dual Positive Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs |
National Semiconductor |
5 |
54LS109J |
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs |
National Semiconductor |
6 |
54LS109M |
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs |
National Semiconductor |
7 |
54LS109N |
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs |
National Semiconductor |
8 |
7470PC |
DC-clocked J-K FLIP-FLOP, one J̅-Input, one K̅-input, two J-Inputs, two K-Inputs |
TUNGSRAM |
9 |
9093 |
DTL integrated circuit, Dual Clocked J-K Flip-Flops, Extended/Standard temperature range |
SGS-ATES |
10 |
9094 |
DTL integrated circuit, Dual Clocked J-K Flip-Flops, Extended/Standard temperature range |
SGS-ATES |
11 |
9097 |
DTL integrated circuit, Dual Clocked J-K Flip-Flops, Extended/Standard temperature range |
SGS-ATES |
12 |
9099 |
DTL integrated circuit, Dual Clocked J-K Flip-Flops, Extended/Standard temperature range |
SGS-ATES |
13 |
CD4095BMS |
CMOS Gated J-K Master-Slave Flip-Flops |
Intersil |
14 |
CD4096BMS |
CMOS Gated J-K Master-Slave Flip-Flops |
Intersil |
15 |
CD4096BMSFN3331 |
Radiation Hardened CMOS Gated J-K Master-Slave Flip-Flops |
Intersil |
16 |
CD54AC109 |
Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
17 |
CD54AC109F3A |
Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
18 |
CD54AC112 |
Dual Negative Edge Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
19 |
CD54AC112F3A |
Dual Negative Edge Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
20 |
CD54ACT109 |
Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
21 |
CD54ACT109F3A |
Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
22 |
CD54ACT112 |
Dual Negative Edge Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
23 |
CD54ACT112F3A |
Dual Negative Edge Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
24 |
CD74AC109 |
Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
25 |
CD74AC109E |
Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
26 |
CD74AC109EE4 |
Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
Texas Instruments |
27 |
CD74AC109M96 |
Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
28 |
CD74AC112 |
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
29 |
CD74AC112E |
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
30 |
CD74AC112EE4 |
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
Texas Instruments |
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