| No. |
Part Name |
Description |
Manufacturer |
| 1 |
10ELS1 |
FRD |
Nihon |
| 2 |
125LS10 |
AC Line Rated Disc Capacitors |
Vishay |
| 3 |
125LS15 |
AC Line Rated Disc Capacitors |
Vishay |
| 4 |
125LS18 |
AC Line Rated Disc Capacitors |
Vishay |
| 5 |
20VLS10 |
AC Line Rated Disc Capacitors |
Vishay |
| 6 |
29LS18 |
Quad D Register With Standard and Three-State Outputs |
Monolithic Memories |
| 7 |
440LS10 |
AC Line Rated Disc Capacitors |
Vishay |
| 8 |
54LS10 |
Triple 3-Input NAND Gate |
Fairchild Semiconductor |
| 9 |
54LS10 |
Triple 3-Input NAND Gates |
IPRS Baneasa |
| 10 |
54LS10 |
Triple 3-Input NAND Gates |
IPRS Baneasa |
| 11 |
54LS10 |
Triple 3-Input NAND Gate |
National Semiconductor |
| 12 |
54LS107 |
Dual JK Flip-Flop (With Separate Clears and Clocks) |
Fairchild Semiconductor |
| 13 |
54LS109 |
Dual JK̅ Positive Edge-Triggered Flip-Flop |
Fairchild Semiconductor |
| 14 |
54LS109 |
Dual Positive Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs |
National Semiconductor |
| 15 |
54LS109DMQB |
7 V, dual positive-edge-triggered master-slave J-K flip-flop with preset, clear and complementary output |
National Semiconductor |
| 16 |
54LS109FMQB |
7 V, dual positive-edge-triggered master-slave J-K flip-flop with preset, clear and complementary output |
National Semiconductor |
| 17 |
54LS109J |
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs |
National Semiconductor |
| 18 |
54LS109M |
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs |
National Semiconductor |
| 19 |
54LS109N |
Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs |
National Semiconductor |
| 20 |
54LS10E |
Triple 3-Input NAND Gates |
National Semiconductor |
| 21 |
54LS10J |
Triple 3-Input NAND Gates |
National Semiconductor |
| 22 |
54LS10M |
Triple 3-Input NAND Gates |
National Semiconductor |
| 23 |
54LS10N |
Triple 3-Input NAND Gates |
National Semiconductor |
| 24 |
54LS10W |
Triple 3-Input NAND Gates |
National Semiconductor |
| 25 |
54LS11 |
Triple 3-Input AND gate |
Fairchild Semiconductor |
| 26 |
54LS11 |
Triple 3-Input AND gates |
IPRS Baneasa |
| 27 |
54LS11 |
Triple 3-Input AND Gates |
IPRS Baneasa |
| 28 |
54LS11 |
Triple 3-Input AND Gate |
National Semiconductor |
| 29 |
54LS112 |
Dual JK Negative Edge-Triggered Flip-Flop |
Fairchild Semiconductor |
| 30 |
54LS112 |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear and Complementary OP |
National Semiconductor |
| | | |
