| No. |
Part Name |
Description |
Manufacturer |
| 121 |
CHL8102-00CRT |
Dual Loop, 2+1 multiphase PWM high density DDR VR solutions with VR12 SVID |
International Rectifier |
| 122 |
CHL8113 |
3 phase PWM high density DDR VR solutions with VR12 SVID |
International Rectifier |
| 123 |
CHL8113-00CRT |
3 phase PWM high density DDR VR solutions with VR12 SVID |
International Rectifier |
| 124 |
CM3107-12SH |
2 Amp Source/ Sink Bus Termination Regulator for DDR Memory and Front Side Bus Applications |
California Micro Devices Corp |
| 125 |
CM310701S |
2 Amp Source/ Sink Bus Termination Regulator for DDR Memory and Front Side Bus Applications |
California Micro Devices Corp |
| 126 |
CM3109 |
2.0A Source/Sink Bus Termination Regulator for Front Side Bus and DDR Memory Bus Termination |
California Micro Devices Corp |
| 127 |
CM3109-00SB |
2.0A Source/Sink Bus Termination Regulator for Front Side Bus and DDR Memory Bus Termination |
California Micro Devices Corp |
| 128 |
CM3109-00SH |
2.0A Source/Sink Bus Termination Regulator for Front Side Bus and DDR Memory Bus Termination |
California Micro Devices Corp |
| 129 |
CSPDDR100 |
CHIP SCALE DDR TERMINATION ARRAY |
California Micro Devices Corp |
| 130 |
CY28341 |
Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems |
Cypress |
| 131 |
CY28341-2 |
Universal Single Chip Clock Solution for VIA™ P4M266/KM266 DDR Systems |
Cypress |
| 132 |
CY28341-3 |
Universal Clock Chip for VIA\P4M/KT/KM400A DDR Systems |
Cypress |
| 133 |
CY28341OC-2 |
Universal Single Chip Clock Solution for VIA™ P4M266/KM266 DDR Systems |
Cypress |
| 134 |
CY28341OC-3 |
Universal Clock Chip for VIA\P4M/KT/KM400A DDR Systems |
Cypress |
| 135 |
CY28341ZC-2 |
Universal Single Chip Clock Solution for VIA™ P4M266/KM266 DDR Systems |
Cypress |
| 136 |
CY28341ZC-3 |
Universal Clock Chip for VIA\P4M/KT/KM400A DDR Systems |
Cypress |
| 137 |
CY28347 |
Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
Cypress |
| 138 |
CY28347OC |
Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
Cypress |
| 139 |
CY28347OCT |
Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
Cypress |
| 140 |
CY28347ZC |
Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
Cypress |
| 141 |
CY28347ZCT |
Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
Cypress |
| 142 |
CY28354-400 |
273-MHz 24-Output Buffer for Four DDR DIMMS for VIA Chipsets Support |
Cypress |
| 143 |
CY7C1148KV18-400BZC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 144 |
CY7C1148KV18-400BZXC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 145 |
CY7C1148KV18-450BZXC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 146 |
CY7C1150KV18-400BZXC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 147 |
CY7C1150KV18-400BZXI |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 148 |
CY7C1168KV18-400BZXC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 149 |
CY7C1168KV18-450BZXC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 150 |
CY7C1168KV18-550BZXC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| | | |
