| No. |
Part Name |
Description |
Manufacturer |
| 241 |
CY7C2665KV18-550BZXC |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 242 |
CY7C2665KV18-550BZXI |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 243 |
CY7C2670KV18-450BZI |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 244 |
CY7C2670KV18-550BZI |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 245 |
CY7C2670KV18-550BZXI |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 246 |
TC7135 |
The TC7135 4-1/2 digit analog-to-digital converter (ADC) offers 50 ppm (1 part in 20,000)resolution with a maximum nonlinearity error of 1 count.An auto-zero cycle reduces zero error to below 10 µV and zero drift to 0.5 µV/° |
Microchip |
| 247 |
TMS418160A-50DZ |
1048576 by 16 bit dynamic random-access memory, single 5-V power supply, 1024-cycle refresh in 16 ms, 50 ns |
Texas Instruments |
| 248 |
TMS418160A-60DZ |
1048576 by 16 bit dynamic random-access memory, single 5-V power supply, 1024-cycle refresh in 16 ms, 60 ns |
Texas Instruments |
| 249 |
TMS418160A-70DZ |
1048576 by 16 bit dynamic random-access memory, single 5-V power supply, 1024-cycle refresh in 16 ms, 70 ns |
Texas Instruments |
| 250 |
U6084B |
PWM Power Control with Automatic Duty-cycle Reduction |
Atmel |
| 251 |
U6084B |
PWM Power Control with Automatic Duty Cycle Reduction |
TEMIC |
| 252 |
U6084B-FP |
PWM Power Control with Automatic Duty-cycle Reduction |
Atmel |
| 253 |
U6084B-FP |
PWM Power Control with Automatic Duty Cycle Reduction |
TEMIC |
| | | |
