| No. |
Part Name |
Description |
Manufacturer |
| 271 |
AH183-PLB |
V(cc): 7V; 230-550mW; low power hall effect latch. For cover detector, speed measurement, home safety |
Anachip |
| 272 |
AH183-W |
V(cc): 7V; 230-550mW; low power hall effect latch. For cover detector, speed measurement, home safety |
Anachip |
| 273 |
AH183-WA |
V(cc): 7V; 230-550mW; low power hall effect latch. For cover detector, speed measurement, home safety |
Anachip |
| 274 |
AH183-WL |
V(cc): 7V; 230-550mW; low power hall effect latch. For cover detector, speed measurement, home safety |
Anachip |
| 275 |
AH183-WLA |
V(cc): 7V; 230-550mW; low power hall effect latch. For cover detector, speed measurement, home safety |
Anachip |
| 276 |
B511N |
Temperature-current converter=-550...+125°C |
RFT |
| 277 |
CY7C1163KV18-550BZC |
18-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 278 |
CY7C1165KV18-550BZC |
18-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 279 |
CY7C1165KV18-550BZXC |
18-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 280 |
CY7C1168KV18-550BZXC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 281 |
CY7C1170KV18-550BZC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 282 |
CY7C1263KV18-550BZXC |
36-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 283 |
CY7C1265KV18-550BZC |
36-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 284 |
CY7C1265KV18-550BZXC |
36-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 285 |
CY7C1268KV18-550BZXC |
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 286 |
CY7C1565KV18-550BZXC |
72-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 287 |
CY7C1568KV18-550BZXC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 288 |
CY7C1568KV18-550BZXI |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 289 |
CY7C1570KV18-550BZXC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 290 |
CY7C1570KV18-550BZXI |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 291 |
CY7C1663KV18-550BZXC |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 292 |
CY7C1665KV18-550BZXC |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 293 |
CY7C1668KV18-550BZXC |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 294 |
CY7C1670KV18-550BZXC |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 295 |
CY7C2163KV18-550BZXI |
18-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 296 |
CY7C2165KV18-550BZC |
18-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 297 |
CY7C2165KV18-550BZXC |
18-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 298 |
CY7C2168KV18-550BZC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 299 |
CY7C2170KV18-550BZXC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 300 |
CY7C2263KV18-550BZXC |
36-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| | | |
