| No. |
Part Name |
Description |
Manufacturer |
| 271 |
CY7C25632KV18-550BZXI |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 272 |
CY7C2564XV18-450BZC |
72-Mbit QDR� II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 273 |
CY7C2564XV18-450BZXC |
72-Mbit QDR� II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 274 |
CY7C25652KV18-450BZC |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 275 |
CY7C25652KV18-450BZI |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 276 |
CY7C25652KV18-450BZXC |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 277 |
CY7C25652KV18-550BZXC |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 278 |
CY7C25652KV18-550BZXI |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 279 |
CY7C25682KV18-550BZXC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 280 |
CY7C25682KV18-550BZXI |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 281 |
CY7C25702KV18-550BZXC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 282 |
CY7C25702KV18-550BZXI |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 283 |
CY7C2663KV18-450BZI |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 284 |
CY7C2663KV18-450BZXC |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 285 |
CY7C2663KV18-550BZI |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 286 |
CY7C2663KV18-550BZXC |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 287 |
CY7C2663KV18-550BZXI |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 288 |
CY7C2665KV18-450BZI |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 289 |
CY7C2665KV18-450BZXI |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 290 |
CY7C2665KV18-550BZI |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 291 |
CY7C2665KV18-550BZXC |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 292 |
CY7C2665KV18-550BZXI |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 293 |
CY7C2670KV18-450BZI |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 294 |
CY7C2670KV18-550BZI |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 295 |
CY7C2670KV18-550BZXI |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 296 |
M393T2950BZ0-CD5/CC |
DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb B-die 72-bit ECC |
Samsung Electronic |
| 297 |
M393T2950BZ3-CD5/CC |
DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb B-die 72-bit ECC |
Samsung Electronic |
| 298 |
MAX6316LUK50BZ-T |
Microprocessor supervisory circuit with watchdog and manual reset (watchdog input,manual reset input,reset output active-low,push/pull).Factory-trimmed reset threshold (typ) 5.000V, min reser timeout 20ms, typ watchdog timeout 25.6sec. |
MAXIM - Dallas Semiconductor |
| 299 |
MAX6316MUK50BZ-T |
Microprocessor supervisory circuit with watchdog and manual reset (watchdog input,manual reset input,reset output active-low,bidirectional).Factory-trimmed reset threshold (typ) 5.000V, min reset timeout 20ms, typ watchdog timeout 25.6sec |
MAXIM - Dallas Semiconductor |
| 300 |
MAX6317HUK50BZ-T |
Microprocessor supervisory circuit with watchdog and manual reset (watchdog input,manual reset input,reset output active-high, push/pull).Factory-trimmed reset threshold (typ) 5.000V, min reset timeout 20ms, typ watchdog timeout 25.6sec |
MAXIM - Dallas Semiconductor |
| | | |
