| No. |
Part Name |
Description |
Manufacturer |
| 31 |
CY7C1548KV18-400BZC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 32 |
CY7C1548KV18-400BZXC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 33 |
CY7C1550KV18-400BZC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 34 |
CY7C1550KV18-400BZXC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 35 |
CY7C1643KV18-400BZC |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 36 |
CY7C1643KV18-400BZXC |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 37 |
CY7C1643KV18-450BZC |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 38 |
CY7C1643KV18-450BZI |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 39 |
CY7C1645KV18-400BZXI |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 40 |
CY7C1645KV18-450BZXI |
144-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 41 |
CY7C1648KV18-400BZXC |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 42 |
CY7C1650KV18-400BZC |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 43 |
CY7C1650KV18-450BZC |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
Cypress |
| 44 |
CY7C2245KV18-450BZXI |
36-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT |
Cypress |
| 45 |
CY7C25422KV18-333BZXC |
72-Mbit QDR� II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT |
Cypress |
| 46 |
CY7C25442KV18-300BZI |
72-Mbit QDR� II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT |
Cypress |
| 47 |
CY7C25442KV18-333BZI |
72-Mbit QDR� II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT |
Cypress |
| 48 |
CY7C25442KV18-333BZXI |
72-Mbit QDR� II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT |
Cypress |
| 49 |
CY7C2642KV18-333BZXC |
144-Mbit QDR� II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT |
Cypress |
| 50 |
CY7C2644KV18-300BZI |
144-Mbit QDR� II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT |
Cypress |
| 51 |
CY7C2644KV18-333BZI |
144-Mbit QDR� II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT |
Cypress |
| 52 |
ISL12030 |
Low Power RTC with 50/60 Cycle AC Input, Alarms and Daylight Savings Correction |
Intersil |
| 53 |
ISL12032 |
Low Power RTC with Battery Backed SRAM and 50/60 Cycle AC Input and Xtal Back-up |
Intersil |
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