No. |
Part Name |
Description |
Manufacturer |
31 |
CDCLVC1108PW |
Low Jitter, 1:8 LVCMOS Fan-out Clock Buffer 16-TSSOP -40 to 85 |
Texas Instruments |
32 |
CDCLVC1108PWR |
Low Jitter, 1:8 LVCMOS Fan-out Clock Buffer 16-TSSOP -40 to 85 |
Texas Instruments |
33 |
CDCLVC1110 |
Low Jitter, 1:10 LVCMOS Fan-out Clock Buffer 20-TSSOP -40 to 85 |
Texas Instruments |
34 |
CDCLVC1110PW |
Low Jitter, 1:10 LVCMOS Fan-out Clock Buffer 20-TSSOP -40 to 85 |
Texas Instruments |
35 |
CDCLVC1110PWR |
Low Jitter, 1:10 LVCMOS Fan-out Clock Buffer 20-TSSOP -40 to 85 |
Texas Instruments |
36 |
CDCLVC1112 |
Low Jitter, 1:12 LVCMOS Fan-out Clock Buffer |
Texas Instruments |
37 |
CDCLVC1112PW |
Low Jitter, 1:12 LVCMOS Fan-out Clock Buffer 24-TSSOP -40 to 85 |
Texas Instruments |
38 |
CDCLVC1112PWR |
Low Jitter, 1:12 LVCMOS Fan-out Clock Buffer 24-TSSOP -40 to 85 |
Texas Instruments |
39 |
IDT74LVC112A |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5V TOLERANT I/O |
IDT |
40 |
IDT74LVC112APG |
3.3V CMOS Dual Negative-Edge-Triggered J-K Flip-Flop with Clear and Preset, 5.0V Tolerant I/O |
IDT |
41 |
IDT74LVC112APG8 |
3.3V CMOS Dual Negative-Edge-Triggered J-K Flip-Flop with Clear and Preset, 5.0V Tolerant I/O |
IDT |
42 |
IDT74LVC11A |
3.3V CMOS TRIPLE 3-INPUT AND GATE WITH 5 VOLT TOLERANT I/O |
IDT |
43 |
IDT74LVC11ADC |
3.3V CMOS Triple 3-Input and GATE with 5.0V Tolerant I/O |
IDT |
44 |
IDT74LVC11ADC8 |
3.3V CMOS Triple 3-Input and GATE with 5.0V Tolerant I/O |
IDT |
45 |
IDT74LVC11APG |
3.3V CMOS Triple 3-Input and GATE with 5.0V Tolerant I/O |
IDT |
46 |
IDT74LVC11APG8 |
3.3V CMOS Triple 3-Input and GATE with 5.0V Tolerant I/O |
IDT |
47 |
IDT74LVC11APGG |
3.3V CMOS Triple 3-Input and GATE with 5.0V Tolerant I/O |
IDT |
48 |
IDT74LVC11APGG8 |
3.3V CMOS Triple 3-Input and GATE with 5.0V Tolerant I/O |
IDT |
49 |
IDT74LVC11APY |
3.3V CMOS Triple 3-Input and GATE with 5.0V Tolerant I/O |
IDT |
50 |
IDT74LVC11APY8 |
3.3V CMOS Triple 3-Input and GATE with 5.0V Tolerant I/O |
IDT |
51 |
LVC11 |
Triple 3-input AND gate |
Philips |
52 |
SN74LVC112A |
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset |
Texas Instruments |
53 |
SN74LVC112AD |
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset |
Texas Instruments |
54 |
SN74LVC112ADBLE |
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset |
Texas Instruments |
55 |
SN74LVC112ADBR |
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset |
Texas Instruments |
56 |
SN74LVC112ADG4 |
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SOIC -40 to 125 |
Texas Instruments |
57 |
SN74LVC112ADGVR |
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset |
Texas Instruments |
58 |
SN74LVC112ADGVRG4 |
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-TVSOP -40 to 125 |
Texas Instruments |
59 |
SN74LVC112ADR |
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset |
Texas Instruments |
60 |
SN74LVC112ADT |
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset |
Texas Instruments |
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