| No. |
Part Name |
Description |
Manufacturer |
| 481 |
BTA216B-500B |
Triacs high commutation |
Philips |
| 482 |
BTA216X-500B |
Three quadrant triacs high commutation |
Philips |
| 483 |
BTA225-500B |
Three quadrant triacs high commutation |
Philips |
| 484 |
BTA225B-500B |
Three quadrant triacs high commutation |
Philips |
| 485 |
BUK638-500B |
PowerMOS transistor Fast recovery diode FET |
Philips |
| 486 |
CXD2500BQ |
CD Digital Signal Processor |
SONY |
| 487 |
CY7C1263KV18-500BZXC |
36-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 488 |
CY7C15632KV18-500BZXI |
72-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 489 |
CY7C1565KV18-500BZC |
72-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 490 |
CY7C1565KV18-500BZI |
72-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 491 |
CY7C1565KV18-500BZXC |
72-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 492 |
CY7C1565KV18-500BZXI |
72-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 493 |
CY7C1568KV18-500BZXI |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 494 |
CY7C1570KV18-500BZC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 495 |
CY7C1570KV18-500BZXC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 496 |
CY7C1570KV18-500BZXI |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
| 497 |
CY7C25632KV18-500BZC |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 498 |
CY7C25632KV18-500BZXC |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 499 |
CY7C25632KV18-500BZXI |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 500 |
CY7C25652KV18-500BZC |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 501 |
CY7C25652KV18-500BZI |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 502 |
CY7C25652KV18-500BZXC |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 503 |
CY7C25652KV18-500BZXI |
72-Mbit QDR�II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 504 |
CY7C25682KV18-500BZC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 505 |
CY7C25702KV18-500BZC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 506 |
CY7C25702KV18-500BZXC |
72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT |
Cypress |
| 507 |
DDU4C-5500B2 |
5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C) |
Data Delay Devices Inc |
| 508 |
DDU4F-5500B2 |
5-TAP, TTL-interfaced fixed delay line |
Data Delay Devices Inc |
| 509 |
DDU7C-500B3 |
10-TAP, TTL-INTERFACED FIXED DELAY LINE |
Data Delay Devices Inc |
| 510 |
DDU7F-500B2 |
10-TAP, TTL-interfaced fixed delay line |
Data Delay Devices Inc |
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