No. |
Part Name |
Description |
Manufacturer |
91 |
BUK9628-55A |
N-channel TrenchMOS logic level FET |
Nexperia |
92 |
BUK9628-55A |
N-channel TrenchMOS logic level FET |
NXP Semiconductors |
93 |
BUK9628-55A |
TrenchMOS(tm) standard level FET |
Philips |
94 |
BUK9728-55A |
BUK9728-55A; N-channel Trenchmos (tm) logic level FET |
Philips |
95 |
BUK9728-55A |
BUK9728-55A; N-channel Trenchmos (tm) logic level FET |
Philips |
96 |
BUK9728-55A |
N-channel Trenchmos (tm) logic level FET |
Philips |
97 |
BUK9E08-55B |
N-channel TrenchMOS logic level FET |
Nexperia |
98 |
BUK9E08-55B |
N-channel TrenchMOS logic level FET |
NXP Semiconductors |
99 |
BUK9E08-55B |
Trenchmos (tm) logic level FET |
Philips |
100 |
CS218-55B |
Leaded Thyristor SCR |
Central Semiconductor |
101 |
CS218-55D |
Leaded Thyristor SCR |
Central Semiconductor |
102 |
CS218-55M |
Leaded Thyristor SCR |
Central Semiconductor |
103 |
CS218-55N |
Leaded Thyristor SCR |
Central Semiconductor |
104 |
CS218-55P |
Leaded Thyristor SCR |
Central Semiconductor |
105 |
CS218-55PB |
Leaded Thyristor SCR |
Central Semiconductor |
106 |
CY62128-55SC |
128K x 8 Static RAM |
Cypress |
107 |
CY62128-55SC |
128K x 8 static RAM, standby current 10mA, 55ns |
Cypress |
108 |
CY62128-55VC |
128K x 8 static RAM, standby current 10mA, 55ns |
Cypress |
109 |
CY62128-55VC |
128K x 8 Static RAM |
Cypress |
110 |
CY62128-55ZC |
128K x 8 Static RAM |
Cypress |
111 |
CY62167G18-55BVXIES |
16-Mbit (1 M words � 16 bit / 2 M words � 8 bit) Static RAM with Error-Correcting Code (ECC) |
Cypress |
112 |
CY7C1163KV18-550BZC |
18-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
113 |
CY7C1165KV18-550BZC |
18-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
114 |
CY7C1165KV18-550BZXC |
18-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
115 |
CY7C1168KV18-550BZXC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
116 |
CY7C1170KV18-550BZC |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
117 |
CY7C1263KV18-550BZXC |
36-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
118 |
CY7C1265KV18-550BZC |
36-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
119 |
CY7C1265KV18-550BZXC |
36-Mbit QDR� II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
120 |
CY7C1268KV18-550BZXC |
36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
Cypress |
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