| No. |
Part Name |
Description |
Manufacturer |
| 91 |
CD74AC112EE4 |
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
Texas Instruments |
| 92 |
CD74AC112M |
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
| 93 |
CD74AC112M96 |
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset |
Texas Instruments |
| 94 |
CD74AC112M96G4 |
Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
Texas Instruments |
| 95 |
HD74AC112 |
Dual JK Negative Edge-Triggered Flip-Flop |
Hitachi Semiconductor |
| 96 |
HD74AC112 |
Standard IC>General-Purpose Logics>HD74AC Series |
Renesas |
| 97 |
IN74AC112D |
Dual J-K flip-flop with set and reset high-speed silicon-gate CMOS |
INTEGRAL |
| 98 |
IN74AC112N |
Dual J-K flip-flop with set and reset high-speed silicon-gate CMOS |
INTEGRAL |
| 99 |
MC74AC112D |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
Motorola |
| 100 |
MC74AC112N |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
Motorola |
| 101 |
TC74AC112F |
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR |
TOSHIBA |
| 102 |
TC74AC112FN |
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR |
TOSHIBA |
| 103 |
TC74AC112P |
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR |
TOSHIBA |
| | | |
